1. Field of the Invention
The present invention relates to a ferroelectric gate transistor memory and a method of driving a ferroelectric gate transistor memory, and specifically, to a non-destructive reading method of memory data.
2. Description of the Related Art
Conventionally, there are mainly two types of ferroelectric memories for recording data by utilizing a hysteresis characteristic of the ferroelectric material; the first one is a combination of a ferroelectric capacitor and a transistor for selecting its ferroelectric cell, and the second one is a type in which thin films made of a ferroelectric material are laminated on a semiconductor substrate so as to control the current and resistance.
The second type has a possibility of non-destructively reading out data stored in a memory cell.
This technique is discussed in "Chapter 5, Perspective of lamination technique for ferroelectric thin films and new device" Section 3, Ferroelectric Gate Non-volatile Memory FET-MFS-FET, Masanori OKUYAMA", and will be discussed with reference to FIGS. 10A, 10B and 10C.
In the structure, an n-type well region (not shown), a p-type source region 2, a drain region, a terminal thereof, a ferroelectric thin film 4 and a gate electrode 5 are formed on a semiconductor substrate 1. FIG. 10A shows a polarization state in which the polarization is downward, whereas FIG. 10B is the case where the polarization is upward. When the polarization is upward, a channel is formed as shown in FIG. 10B without applying a voltage to the gate, allowing a drain current to flow as illustrated in FIG. 10C. Such a device having a structure in which the gate of an FET is connected to the ferroelectric this film is called an F gate FET, hereinafter.
An example of a memory device which employs the F gate FET is that shown in FIG. 11, in which memory cells each consisting of combining an F gate FET and MOS-FET, are arranged in matrix (Jap. Pat. Appln. KOKAI Publication No. 5-120866), and another example is that shown in FIG. 12, in which a bit line is provided between the gate of an F gate FET and a ferroelectric member (see Jap. Pat. Appln. KOKAI Publication No. 5-90532).
However, the above-described types of F gate FETs shown FIGS. 10A and 10B, in spite of their advantages, entails the following three major drawbacks.
First, when a writing or erasing operation is performed by applying a voltage between the gate electrode 5 and the semiconductor substrate 1, the voltage must be very high.
Second, in order to select a desired F gate FET, a transistor for selection must be provided, causing an enlargement of the circuit, and resulting in enlargement of the area of the memory cell.
Third, in order to non-destructively read out data from a memory cell, it is necessary to apply a voltage on the source 2 and drain 3; however while applying the voltage on the source 2 and the drain 3, a voltage is inevitably applied between the gate electrode 5 and the source 2 and between the drain 3 and the gate electrode 5, thus erasing the polarization of the ferroelectric capacitor 4 in the memory cell as it repeats.
Meanwhile, the structure shown in FIG. 12 of Jap. Pat. Appln. KOKAI Publication No. 5-90532, is proposed to reduce the voltage for writing, and a word line (Xi word line) 6 and a bit line (Yj data line) 7 are provided in the ferroelectric capacitor 4, and a voltage is directly applied to the ferroelectric capacitor when writing data.
However, these KOKAI publications do not include a specific description of the method for writing or reading data, the biasing method, the selection method, or the sensing method when reading out of data. Nor do they disclose the structure of a memory which controls the potential difference between the source and drain.
Thus, the aforementioned three drawbacks have not been solved by the conventional techniques.